1. Field of the Invention
The present invention relates to method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a capacitor having reduced defects arising during fabrication of the capacitor for the semiconductor device.
2. Description of the Related Art
Recently, as semiconductor users require semiconductor devices having low power use, high storage capacity and high speed features, semiconductor manufacturers have increasingly investigated highly integrated, high-speed semiconductor devices. In particular, a dynamic random access memory (DRAM), which has a free data input/output capability and a large storage capacity, is widely used as a semiconductor memory cell.
Generally, a DRAM is a collection of unit cells, each cell having one MOS transistor and one storage capacitor. The capacitance of a capacitor depends on a thickness of a dielectric film, a dielectric constant, and a contact area between an upper electrode and a lower electrode. As increased integration reduces the size of a semiconductor chip, the size of the capacitor is also reduced. The reduction in capacitor size correspondingly reduces the capacitance and, hence, the storage capacity of a capacitor. Thus, a capacitor having sufficient storage capacity to ensure operation of the semiconductor memory device, even as integration of the semiconductor memory increased, is needed.
One solution involves a capacitor having a one cylinder storage (OCS) structure, in which a total effective area of the capacitor can be increased by increasing a vertical area while reducing a horizontal area occupied by the capacitor in the semiconductor memory cell, resulting in increased storage capacitance.
However, a storage node electrode using a capacitor having the aforementioned OCS structure has a relatively high aspect ratio, i.e., its height is much greater than its width. Such high aspect ratio storage node electrodes tend to lean or collapse. In particular, multi-bit failure occurs when the storage node electrodes are slanted or damaged easily due to surface tension during removal of a mold oxide film formed between the storage node electrodes. Twin-bit failure also occurs when upper portions of neighboring storage node electrodes are in contact with each other. Further, when a buffered oxide etchant (BOE) containing ammonium fluoride (NH4F) is used to remove the mold oxide film, NH4F reacts with water to create OH− ions, which cause defects in the storage node electrodes of a polysilicon material, resulting in property degradation and defects in the semiconductor device. If the storage node electrodes are crystallized to prevent the storage node electrode from leaning or collapsing, or if the storage node electrodes are annealed to form a hemi-spherical grain (HSG) film on the storage node electrodes, defects in the storage node electrodes are further increased during removal of the mold oxide film.
Further, a BOE has a slow etch rate for a doped oxide film. Therefore, when the BOE is used to remove a mold oxide film, a removing process time increases, thereby degrading semiconductor fabrication yield.